[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Javed Absar via llvm-commits]

Hi Michael:

Thanks for the reply. The block diagram gives me some idea of the pipeline
but the waybackmachine page is not accessible either.
 Do you reckon you could send over the pdf as attachment?

Thanks a lot.
Javed

On Fri, 11 Oct 2019 at 19:02, Michael Collison <michael.collison at sifive.com>
wrote:

> There is not a lot of formal documentation on the RISCV Rocket core.
> There is the page from lowrisc:
>
> https://www.lowrisc.org/docs/tagged-memory-v0.1/rocket-core/
>
> and the berkely page:
>
> http://www-inst.eecs.berkeley.edu/~cs250/fa13/handouts/lab2-riscv.pdf#13
>
> Note the latter link appears unreachable at the moment, but you can
> access the pdf from the waybackmachine page (https://archive.org/web).
>
> On 10/11/19 3:22 AM, Javed Absar via Phabricator wrote:
> > javed.absar added a comment.
> >
> > In D68685#1705570 <https://reviews.llvm.org/D68685#1705570>, @rogfer01
> wrote:
> >
> >> @javedabsar (or @javed.absar) I seem to recall you have experience with
> schedulers. If you could give us a hand here that'd be great! :)
> >
> > Sure no problem Roger :)
> >
> > Could you please point me to some doc which describes the pipeline model
> of RISCVRocket64 - i.e. what kind of processing units are available, how
> each instruction flows through the pipeline (fully pipelined or partially,
> latencies, resource dependences)?
> >
> > That would be my starting point to match against the schedules defined
> in schedule*.td.
> >
> >
> > Repository:
> >    rL LLVM
> >
> > CHANGES SINCE LAST ACTION
> >    https://reviews.llvm.org/D68685/new/
> >
> > https://reviews.llvm.org/D68685
> >
> >
> >
>
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