[PATCH] D68685: [RISCV] Scheduler description for Rocket Core

[Luís Marques via Phabricator via llvm-commits]

luismarques added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVSchedRocket32.td:79
+
+// What is the correct latecny to model for fence instructions?
+def : WriteRes<WriteFence, [Rocket32UnitMem]>;
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typo


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  https://reviews.llvm.org/D68685/new/

https://reviews.llvm.org/D68685