[PATCH] D68729: [AMDGPU] Fixed dpp combine of VOP1

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:221-222
       ++NumOperands;
+    } else if (AMDGPU::getNamedOperandIdx(DPPOp,
+                   AMDGPU::OpName::src1_modifiers) != -1) {
+      DPPInst.addImm(0);
----------------
rampitec wrote:
> arsenm wrote:
> > This case isn't tested
> I do not think such instructions currently exists. VOP2 are tested by the original test.
Won't this happen for any VOP2 form of an FP instruction? V_MIN_F32_e32 has no modifiers, but V_MIN_F32_dpp does


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68729/new/

https://reviews.llvm.org/D68729