[PATCH] D68121: [X86] Model MXCSR for all SSE instructions

Fri Sep 27 05:50:19 PDT 2019

pengfei marked an inline comment as done.
pengfei added a comment.

In D68121#1685355 <https://reviews.llvm.org/D68121#1685355>, @craig.topper wrote:

> Does this really not affect any tests? I would have thought some test would print MIR output that would show the implicit use that wasn't there before.

You are correct. Besides some MIR tests, there're also some machine combiner failure. I'm trying to fix it. Thanks for reminding.

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Comment at: llvm/lib/Target/X86/X86InstrFormats.td:230
 class NOTRACK { bit hasNoTrackPrefix = 1; }
+class SIMD_EXP { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; }

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pengfei wrote:
> RKSimon wrote:
> > craig.topper wrote:
> > > Is EXP an abbreviation for Exception? If so, I think EXC is probably a better abbreviation
> > mayRaiseMXCSRException might be better as well - to avoid x87/fpu ambiguity
> mayRaiseFPException is a target independent flag and is widely used to check if an instruction may raise  exception during optimization. I think there's no need to distinguish it from x87 or SIMD during the optimization, and we can distinguish them from the cpcode of MI if necessary.
Yes, I'll change the name.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D68121/new/

https://reviews.llvm.org/D68121