[PATCH] D68121: [X86] Model MXCSR for all SSE instructions

Fri Sep 27 05:47:13 PDT 2019

pengfei marked an inline comment as done.
pengfei added a comment.

In D68121#1685679 <https://reviews.llvm.org/D68121#1685679>, @RKSimon wrote:

> Instead of attributing all these instructions with MXCSR first wouldn't we be better off starting just attributing (V)LDMXCSR/(V)STMXCSR in this patch and then future patches sets up groups of instructions with suitable tests?

The difficult is we may have X87/SSE/AVX/AVX512 instructions under the same node, so I'm planning to mode the attribute of instructions by X87/SSE/AVX/AVX512 first, then set up instructions by node.
And we don't need to model MXCSR for (V)LDMXCSR/(V)STMXCSR, because they are using hasSideEffects and cannot be replaced due to we only modeling rounding and exception bits in MXCSR.

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Comment at: llvm/lib/Target/X86/X86InstrFormats.td:230
 class NOTRACK { bit hasNoTrackPrefix = 1; }
+class SIMD_EXP { list<Register> Uses = [MXCSR]; bit mayRaiseFPException = 1; }

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RKSimon wrote:
> craig.topper wrote:
> > Is EXP an abbreviation for Exception? If so, I think EXC is probably a better abbreviation
> mayRaiseMXCSRException might be better as well - to avoid x87/fpu ambiguity
mayRaiseFPException is a target independent flag and is widely used to check if an instruction may raise  exception during optimization. I think there's no need to distinguish it from x87 or SIMD during the optimization, and we can distinguish them from the cpcode of MI if necessary.

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