[llvm] r372676 - [InstCombine] Fold a shifty implementation of clamp-to-zero.
Huihui Zhang via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 23 17:15:03 PDT 2019
Author: huihuiz
Date: Mon Sep 23 17:15:03 2019
New Revision: 372676
URL: http://llvm.org/viewvc/llvm-project?rev=372676&view=rev
Log:
[InstCombine] Fold a shifty implementation of clamp-to-zero.
Summary:
Fold
and(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X)
into
X s> Y ? X : 0
https://rise4fun.com/Alive/lFH
Fold shift into select enables more optimization,
e.g., vmax generation for ARM target.
Reviewers: lebedev.ri, efriedma, spatel, kparzysz, bcahoon
Reviewed By: lebedev.ri
Subscribers: xbolva00, andreadb, craig.topper, RKSimon, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D67799
Modified:
llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
llvm/trunk/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp?rev=372676&r1=372675&r2=372676&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp Mon Sep 23 17:15:03 2019
@@ -1926,6 +1926,20 @@ Instruction *InstCombiner::visitAnd(Bina
A->getType()->isIntOrIntVectorTy(1))
return SelectInst::Create(A, Op0, Constant::getNullValue(I.getType()));
+ // and(ashr(subNSW(Y, X), ScalarSizeInBits(Y)-1), X) --> X s> Y ? X : 0.
+ {
+ Value *X, *Y;
+ const APInt *ShAmt;
+ Type *Ty = I.getType();
+ if (match(&I, m_c_And(m_OneUse(m_AShr(m_NSWSub(m_Value(Y), m_Value(X)),
+ m_APInt(ShAmt))),
+ m_Deferred(X))) &&
+ *ShAmt == Ty->getScalarSizeInBits() - 1) {
+ Value *NewICmpInst = Builder.CreateICmpSGT(X, Y);
+ return SelectInst::Create(NewICmpInst, X, ConstantInt::getNullValue(Ty));
+ }
+ }
+
return nullptr;
}
Modified: llvm/trunk/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll?rev=372676&r1=372675&r2=372676&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/sub-ashr-and-to-icmp-select.ll Mon Sep 23 17:15:03 2019
@@ -12,9 +12,8 @@
define i8 @sub_ashr_and_i8(i8 %x, i8 %y) {
; CHECK-LABEL: @sub_ashr_and_i8(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i8 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i8 [[SUB]], 7
-; CHECK-NEXT: [[AND:%.*]] = and i8 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i8 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i8 [[X]], i8 0
; CHECK-NEXT: ret i8 [[AND]]
;
%sub = sub nsw i8 %y, %x
@@ -25,9 +24,8 @@ define i8 @sub_ashr_and_i8(i8 %x, i8 %y)
define i16 @sub_ashr_and_i16(i16 %x, i16 %y) {
; CHECK-LABEL: @sub_ashr_and_i16(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i16 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i16 [[SUB]], 15
-; CHECK-NEXT: [[AND:%.*]] = and i16 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i16 [[X]], i16 0
; CHECK-NEXT: ret i16 [[AND]]
;
@@ -39,9 +37,8 @@ define i16 @sub_ashr_and_i16(i16 %x, i16
define i32 @sub_ashr_and_i32(i32 %x, i32 %y) {
; CHECK-LABEL: @sub_ashr_and_i32(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 %y, %x
@@ -52,9 +49,8 @@ define i32 @sub_ashr_and_i32(i32 %x, i32
define i64 @sub_ashr_and_i64(i64 %x, i64 %y) {
; CHECK-LABEL: @sub_ashr_and_i64(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i64 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i64 [[SUB]], 63
-; CHECK-NEXT: [[AND:%.*]] = and i64 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i64 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i64 [[X]], i64 0
; CHECK-NEXT: ret i64 [[AND]]
;
%sub = sub nsw i64 %y, %x
@@ -67,9 +63,8 @@ define i64 @sub_ashr_and_i64(i64 %x, i64
define i32 @sub_ashr_and_i32_nuw_nsw(i32 %x, i32 %y) {
; CHECK-LABEL: @sub_ashr_and_i32_nuw_nsw(
-; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nuw nsw i32 %y, %x
@@ -82,9 +77,8 @@ define i32 @sub_ashr_and_i32_nuw_nsw(i32
define i32 @sub_ashr_and_i32_commute(i32 %x, i32 %y) {
; CHECK-LABEL: @sub_ashr_and_i32_commute(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 %y, %x
@@ -97,9 +91,8 @@ define i32 @sub_ashr_and_i32_commute(i32
define <4 x i32> @sub_ashr_and_i32_vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @sub_ashr_and_i32_vec(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nsw <4 x i32> %y, %x
@@ -110,9 +103,8 @@ define <4 x i32> @sub_ashr_and_i32_vec(<
define <4 x i32> @sub_ashr_and_i32_vec_nuw_nsw(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @sub_ashr_and_i32_vec_nuw_nsw(
-; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nuw nsw <4 x i32> %y, %x
@@ -123,9 +115,8 @@ define <4 x i32> @sub_ashr_and_i32_vec_n
define <4 x i32> @sub_ashr_and_i32_vec_commute(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: @sub_ashr_and_i32_vec_commute(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw <4 x i32> [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 31>
-; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[X]], <4 x i32> zeroinitializer
; CHECK-NEXT: ret <4 x i32> [[AND]]
;
%sub = sub nsw <4 x i32> %y, %x
@@ -140,8 +131,8 @@ define i32 @sub_ashr_and_i32_extra_use_s
; CHECK-LABEL: @sub_ashr_and_i32_extra_use_sub(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
; CHECK-NEXT: store i32 [[SUB]], i32* [[P:%.*]], align 4
-; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[Y]], [[X]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
; CHECK-NEXT: ret i32 [[AND]]
;
%sub = sub nsw i32 %y, %x
@@ -153,9 +144,8 @@ define i32 @sub_ashr_and_i32_extra_use_s
define i32 @sub_ashr_and_i32_extra_use_and(i32 %x, i32 %y, i32* %p) {
; CHECK-LABEL: @sub_ashr_and_i32_extra_use_and(
-; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
-; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
-; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
+; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[AND:%.*]] = select i1 [[TMP1]], i32 [[X]], i32 0
; CHECK-NEXT: store i32 [[AND]], i32* [[P:%.*]], align 4
; CHECK-NEXT: ret i32 [[AND]]
;
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