[PATCH] D67898: [SDAG] Peek through bitcasts before commuting setcc operands

[Pengfei Wang via Phabricator via llvm-commits]

pengfei created this revision.
pengfei added reviewers: spatel, craig.topper, RKSimon, efriedma, jpienaar.
Herald added subscribers: llvm-commits, hiraditya.
Herald added a project: LLVM.

This patch fix a bug result from D63958 <https://reviews.llvm.org/D63958>.

On X86 32 bit, BUILD_VECTOR <2 x i64> will be broke into a combine of BUILD_VECTOR <4 x i32> and bitcast. So we should peek through it, otherwise it may fall into dead loop in some cases. e.g.

  1 define <2 x i64> @test(<2 x i64> %a) {
  2   %1 = sub <2 x i64> zeroinitializer, %a
  3   %2 = icmp eq <2 x i64> %a, zeroinitializer
  4   %3 = select <2 x i1> %2, <2 x i64> %a, <2 x i64> %1
  5   ret <2 x i64> %3
  6 }

llc -mtriple=i686 -matttr=+avx512f -mattr=avx512vl t.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D67898

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3069,7 +3069,8 @@
   // -- but in reverse order -- then try to commute the operands of this setcc
   // to match. A matching pair of setcc (cmp) and sub may be combined into 1
   // instruction on some targets.
-  if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
+  if (!isConstOrConstSplat(peekThroughBitcasts(N0)) &&
+      !isConstOrConstSplat(peekThroughBitcasts(N1)) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
       DAG.getNodeIfExists(ISD::SUB, DAG.getVTList(OpVT), { N1, N0 } ) &&


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