[llvm] r372537 - [X86] Convert to Constant arguments to MMX shift by i32 intrinsics to TargetConstant during lowering.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Sun Sep 22 18:21:51 2019
New Revision: 372537

URL: http://llvm.org/viewvc/llvm-project?rev=372537&view=rev
Log:
[X86] Convert to Constant arguments to MMX shift by i32 intrinsics to TargetConstant during lowering.

This allows us to use timm in the isel table which is more
consistent with other intrinsics that take an immediate now.

We can't declare the intrinsic as taking an ImmArg because we
need to match non-constants to the shift by MMX register
instruction which we do by mutating the intrinsic id during
lowering.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86InstrMMX.td

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=372537&r1=372536&r2=372537&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 22 18:21:51 2019
@@ -23746,10 +23746,14 @@ SDValue X86TargetLowering::LowerINTRINSI
   case Intrinsic::x86_mmx_psrli_q:
   case Intrinsic::x86_mmx_psrai_w:
   case Intrinsic::x86_mmx_psrai_d: {
+    SDLoc DL(Op);
     SDValue ShAmt = Op.getOperand(2);
-    // If the argument is a constant, this is fine.
-    if (isa<ConstantSDNode>(ShAmt))
-      return Op;
+    // If the argument is a constant, convert it to a target constant.
+    if (auto *C = dyn_cast<ConstantSDNode>(ShAmt)) {
+      ShAmt = DAG.getTargetConstant(C->getZExtValue(), DL, MVT::i32);
+      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
+                         Op.getOperand(0), Op.getOperand(1), ShAmt);
+    }
 
     unsigned NewIntrinsic;
     switch (IntNo) {
@@ -23783,7 +23787,6 @@ SDValue X86TargetLowering::LowerINTRINSI
     // The vector shift intrinsics with scalars uses 32b shift amounts but
     // the sse2/mmx shift instructions reads 64 bits. Copy the 32 bits to an
     // MMX register.
-    SDLoc DL(Op);
     ShAmt = DAG.getNode(X86ISD::MMX_MOVW2D, DL, MVT::x86mmx, ShAmt);
     return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, Op.getValueType(),
                        DAG.getConstant(NewIntrinsic, DL, MVT::i32),

Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=372537&r1=372536&r2=372537&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Sep 22 18:21:51 2019
@@ -66,7 +66,7 @@ let Constraints = "$src1 = $dst" in {
     def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
                                    (ins VR64:$src1, i32u8imm:$src2),
                     !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
-           [(set VR64:$dst, (IntId2 VR64:$src1, imm:$src2))]>,
+           [(set VR64:$dst, (IntId2 VR64:$src1, timm:$src2))]>,
            Sched<[schedImm]>;
   }
 }