[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[James Clarke via Phabricator via llvm-commits]

jrtc27 added a comment.

I'm still personally not fond of the `Fx_F`/`Fx_D` convention. The fact that `F0_F` < `F1_F` < `F0_D` < `F1_D` is highly surprising, especially when `F0_32` < `F0_64` < `F1_32` < `F1_64`, and not what one would naively assume. I also don't know whether this peculiarity of TableGen is meant to be something that's relied upon. I know it doesn't match the ISA convention of always calling them `Fx`, but `Fx` and `Dx` have precedence in other backends and do not risk this same confusion. Moreover, the spec itself is highly inconsistent in how to refer to single and double precision floating point:

- The load/store instructions are suffixed with W/D/Q
- Other floating point instructions are suffixed with .S/.D/.Q
- The extensions are F/D/Q

So, personally, I would still vote for `Fx`/`Dx`/`Qx` given it avoids confusion, matches a bunch of other backends, and matches the ISA extension letters.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423