[PATCH] D67423: [RISCV] Rename FPRs and use Register arithmetic

[Sam Elliott via Phabricator via llvm-commits]

lenary added a comment.
Herald added a subscriber: dmgreen.

One suggestion, then LGTM



================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp:31
+static_assert(RISCV::F31_F == RISCV::F0_F + 31, "Register list not consecutive");
+static_assert(RISCV::F18_D == RISCV::F3_D + 15, "Register list not consecutive");
+
----------------
luismarques wrote:
> lenary wrote:
> > Why does this static assert not cover all 31 64-bit FP regs?
> You'd need a static_foreach to really check that all 32 of them are consecutive. Checking R31 == R0 + 31 strictly speaking doesn't check that R1-30 aren't scrambled. Choosing different indices for that last assert was a compromise attempt to both impart that concept and to take the opportunity to check some different indices. There's a precedent for checking other regs than the first and last.
It just looks super weird. How about one static assert to ensure that `F31_D == F0_D + 31`, and then another three asserts to ensure `F1_D = F0_D + 1` for each of the register types. I think worrying that the order is scrambled beyond that is way too conservative.


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  https://reviews.llvm.org/D67423/new/

https://reviews.llvm.org/D67423