[PATCH] D67497: [aarch64] move custom isel of extract_vector_elt to td file - NFC

[Sebastian Pop via Phabricator via llvm-commits]

sebpop added a comment.

In D67497#1667851 <https://reviews.llvm.org/D67497#1667851>, @evandro wrote:

> Is there a test case that checks that this change does not break what the code in `AArch64DAGToDAGISel::Select()` was meant to handle?


Yes, there are several tests relying on this behavior.
If I just comment out the patterns to the TD file, I get all these tests failing:

  Failing Tests (28):
      LLVM :: CodeGen/AArch64/arm64-2012-05-07-DAGCombineVectorExtract.ll
      LLVM :: CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
      LLVM :: CodeGen/AArch64/arm64-crypto.ll
      LLVM :: CodeGen/AArch64/arm64-neon-copy.ll
      LLVM :: CodeGen/AArch64/arm64-popcnt.ll
      LLVM :: CodeGen/AArch64/arm64-smaxv.ll
      LLVM :: CodeGen/AArch64/arm64-sminv.ll
      LLVM :: CodeGen/AArch64/arm64-vaddv.ll
      LLVM :: CodeGen/AArch64/arm64-vmul.ll
      LLVM :: CodeGen/AArch64/bitcast-v2i8.ll
      LLVM :: CodeGen/AArch64/bitreverse.ll
      LLVM :: CodeGen/AArch64/build-vector-extract.ll
      LLVM :: CodeGen/AArch64/div-rem-pair-recomposition-signed.ll
      LLVM :: CodeGen/AArch64/div-rem-pair-recomposition-unsigned.ll
      LLVM :: CodeGen/AArch64/expand-select.ll
      LLVM :: CodeGen/AArch64/extract-insert.ll
      LLVM :: CodeGen/AArch64/sadd_sat_vec.ll
      LLVM :: CodeGen/AArch64/ssub_sat_vec.ll
      LLVM :: CodeGen/AArch64/trunc-v1i64.ll
      LLVM :: CodeGen/AArch64/uadd_sat_vec.ll
      LLVM :: CodeGen/AArch64/usub_sat_vec.ll
      LLVM :: CodeGen/AArch64/vec_uaddo.ll
      LLVM :: CodeGen/AArch64/vec_umulo.ll
      LLVM :: CodeGen/AArch64/vecreduce-add-legalization.ll
      LLVM :: CodeGen/AArch64/vecreduce-and-legalization.ll
      LLVM :: CodeGen/AArch64/vecreduce-bool.ll
      LLVM :: CodeGen/AArch64/vecreduce-umax-legalization.ll


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67497/new/

https://reviews.llvm.org/D67497