[PATCH] D67497: [aarch64] move custom isel of extract_vector_elt to td file - NFC

Sjoerd Meijer via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 12 08:03:34 PDT 2019


SjoerdMeijer added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:6978
+                                                SDTCisVT<2, i64>]>;
+def kextract : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDT_ExtractVectorElt>;
+
----------------
sebpop wrote:
> SjoerdMeijer wrote:
> > We were curious why you need a new AArch64 specific DAG node?  Can you not use `extractelt` in the match patterns?
> I did that because two other targets do that: git grep says
> ```
> SystemZ/SystemZOperators.td:def z_vector_extract    : SDNode<"ISD::EXTRACT_VECTOR_ELT",
> X86/X86InstrAVX512.td:def X86kextract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
> ```
> 
> I tried replacing kextract with extractelt and I got this error:
> ```
> Type set is empty for each HW mode:
> possible type contradiction in the pattern below (use -print-records with llvm-tblgen to see all expanded records).
> vtInt: 	(vt:{ *:[Other] })
> ```
> I still need to see how to solve this error.
Okay, now I see where the name `kextract` comes from :-)
Before wondering why we need another node, I was wondering what it could mean, and wanted to add that as a nitpick.

That useless tablegen error doesn't ring a bell.... I mean, I have seen it before and then the type contradiction was obvious, but in this case I am a bit clueless. 


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D67497/new/

https://reviews.llvm.org/D67497





More information about the llvm-commits mailing list