[PATCH] D63973: [MachineVerifier] Improve checks of target instructions operands.

[Dean Michael Berris via Phabricator via llvm-commits]

dberris added a comment.

In D63973#1645986 <https://reviews.llvm.org/D63973#1645986>, @thegameg wrote:

> Thanks, this LGTM. I quickly looked at the X86 tests, it seems that `PATCHABLE_EVENT_CALL` and `PATCHABLE_TYPED_EVENT_CALL` are always created with a register but expect immediates in `Target.td`. I'm not sure what was the intention so I'll leave it to @dberris.


The intention is to have the arguments always be in a specific set of registers because the trampolines for XRay expect those to be in specific registers. I wasn't sure how to achieve this consistently and correctly in the lowering. Any pointers here would be really helpful to me too as I have very limited understanding of the MIR validation to achieve what I was hoping for.


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