[PATCH] D64944: [GlobalISel][AArch64] Add support for base register + offset register loads

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: Petar.Avramovic, jfb, hiraditya, kristof.beyls, javed.absar, rovka.
Herald added a project: LLVM.

Add support for folding G_GEPs into loads of the form

  ldr reg, [base, off]

when possible. This can save an add before the load. Currently, this is only supported for loads of 64 bits into 64 bit registers.

Add a new addressing mode function, `selectAddrModeRegisterOffset` which performs this folding when it is profitable.

Also add a test for addressing modes for G_LOAD.


https://reviews.llvm.org/D64944

Files:
  llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir

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