[PATCH] D64338: TableGen: Add address space to matchers

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: dsanders.
Herald added subscribers: jfb, tpr, wdng.

Currently AMDGPU uses a CodePatPred to check address spaces from the
MachineMemOperand. Introduce a new first class property so that the
existing patterns can be easily modified to uses the new generated
predicate, which will also be handled for GlobalISel.

      

I would prefer these to match against the pointer type of the
instruction, but that would be difficult to get working with
SelectionDAG compatbility. This is much easier for now and will avoid
a painful tablegen rewrite for all the loads and stores.

     

I'm also not sure if there's a better way to encode multiple address
spaces in the table, rather than putting the number to expect.


https://reviews.llvm.org/D64338

Files:
  include/llvm/CodeGen/GlobalISel/InstructionSelector.h
  include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  include/llvm/Target/TargetSelectionDAG.td
  test/TableGen/address-space-patfrags.td
  utils/TableGen/CodeGenDAGPatterns.cpp
  utils/TableGen/CodeGenDAGPatterns.h
  utils/TableGen/GlobalISelEmitter.cpp

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