[llvm] r365321 - [AMDGPU][MC] Corrected parsing of FLAT offset modifier
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 8 07:27:38 PDT 2019
Author: dpreobra
Date: Mon Jul 8 07:27:37 2019
New Revision: 365321
URL: http://llvm.org/viewvc/llvm-project?rev=365321&view=rev
Log:
[AMDGPU][MC] Corrected parsing of FLAT offset modifier
Summary of changes:
- simplified handling of FLAT offset: offset_s13 and offset_u12 have been replaced with flat_offset;
- provided information about error position for pre-gfx9 targets;
- improved errors handling.
Reviewers: artem.tamazov, arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D64244
Modified:
llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
llvm/trunk/test/MC/AMDGPU/flat-gfx10.s
llvm/trunk/test/MC/AMDGPU/flat-gfx9.s
llvm/trunk/test/MC/AMDGPU/flat-global.s
llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s
Modified: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp Mon Jul 8 07:27:37 2019
@@ -316,8 +316,7 @@ public:
bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
- bool isOffsetU12() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isUInt<12>(getImm()); }
- bool isOffsetS13() const { return (isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset)) && isInt<13>(getImm()); }
+ bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); }
bool isGDS() const { return isImmTy(ImmTyGDS); }
bool isLDS() const { return isImmTy(ImmTyLDS); }
bool isDLC() const { return isImmTy(ImmTyDLC); }
@@ -1154,15 +1153,17 @@ private:
const SMLoc Loc);
bool parseHwregBody(OperandInfoTy &HwReg, int64_t &Offset, int64_t &Width);
- void validateHwreg(const OperandInfoTy &HwReg,
+ bool validateHwreg(const OperandInfoTy &HwReg,
const int64_t Offset,
const int64_t Width,
const SMLoc Loc);
void errorExpTgt();
OperandMatchResultTy parseExpTgtImpl(StringRef Str, uint8_t &Val);
+ SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
- bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc);
+ bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
+ bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
bool validateSOPLiteral(const MCInst &Inst) const;
bool validateConstantBusLimitations(const MCInst &Inst);
bool validateEarlyClobberLimitations(const MCInst &Inst);
@@ -1238,8 +1239,7 @@ public:
AMDGPUOperand::Ptr defaultSMRDOffset8() const;
AMDGPUOperand::Ptr defaultSMRDOffset20() const;
AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
- AMDGPUOperand::Ptr defaultOffsetU12() const;
- AMDGPUOperand::Ptr defaultOffsetS13() const;
+ AMDGPUOperand::Ptr defaultFlatOffset() const;
OperandMatchResultTy parseOModOperand(OperandVector &Operands);
@@ -2437,28 +2437,6 @@ unsigned AMDGPUAsmParser::checkTargetMat
}
}
- if (TSFlags & SIInstrFlags::FLAT) {
- // FIXME: Produces error without correct column reported.
- auto Opcode = Inst.getOpcode();
- auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
-
- const auto &Op = Inst.getOperand(OpNum);
- if (!hasFlatOffsets() && Op.getImm() != 0)
- return Match_InvalidOperand;
-
- // GFX10: Address offset is 12-bit signed byte offset. Must be positive for
- // FLAT segment. For FLAT segment MSB is ignored and forced to zero.
- if (isGFX10()) {
- if (TSFlags & SIInstrFlags::IsNonFlatSeg) {
- if (!isInt<12>(Op.getImm()))
- return Match_InvalidOperand;
- } else {
- if (!isUInt<11>(Op.getImm()))
- return Match_InvalidOperand;
- }
- }
- }
-
return Match_Success;
}
@@ -3007,6 +2985,55 @@ bool AMDGPUAsmParser::validateLdsDirect(
return (Desc.TSFlags & SIInstrFlags::SDWA) == 0 && !IsRevOpcode(Opcode);
}
+SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
+ for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
+ AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
+ if (Op.isFlatOffset())
+ return Op.getStartLoc();
+ }
+ return getLoc();
+}
+
+bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
+ const OperandVector &Operands) {
+ uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
+ if ((TSFlags & SIInstrFlags::FLAT) == 0)
+ return true;
+
+ auto Opcode = Inst.getOpcode();
+ auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
+ assert(OpNum != -1);
+
+ const auto &Op = Inst.getOperand(OpNum);
+ if (!hasFlatOffsets() && Op.getImm() != 0) {
+ Error(getFlatOffsetLoc(Operands),
+ "flat offset modifier is not supported on this GPU");
+ return false;
+ }
+
+ // Address offset is 12-bit signed for GFX10, 13-bit for GFX9.
+ // For FLAT segment the offset must be positive;
+ // MSB is ignored and forced to zero.
+ unsigned OffsetSize = isGFX9() ? 13 : 12;
+ if (TSFlags & SIInstrFlags::IsNonFlatSeg) {
+ if (!isIntN(OffsetSize, Op.getImm())) {
+ Error(getFlatOffsetLoc(Operands),
+ isGFX9() ? "expected a 13-bit signed offset" :
+ "expected a 12-bit signed offset");
+ return false;
+ }
+ } else {
+ if (!isUIntN(OffsetSize - 1, Op.getImm())) {
+ Error(getFlatOffsetLoc(Operands),
+ isGFX9() ? "expected a 12-bit unsigned offset" :
+ "expected an 11-bit unsigned offset");
+ return false;
+ }
+ }
+
+ return true;
+}
+
bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
unsigned Opcode = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opcode);
@@ -3097,7 +3124,8 @@ bool AMDGPUAsmParser::validateVOP3Litera
}
bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
- const SMLoc &IDLoc) {
+ const SMLoc &IDLoc,
+ const OperandVector &Operands) {
if (!validateLdsDirect(Inst)) {
Error(IDLoc,
"invalid use of lds_direct");
@@ -3163,6 +3191,9 @@ bool AMDGPUAsmParser::validateInstructio
"invalid image_gather dmask: only one bit must be set");
return false;
}
+ if (!validateFlatOffset(Inst, Operands)) {
+ return false;
+ }
return true;
}
@@ -3203,7 +3234,7 @@ bool AMDGPUAsmParser::MatchAndEmitInstru
switch (Result) {
default: break;
case Match_Success:
- if (!validateInstruction(Inst, IDLoc)) {
+ if (!validateInstruction(Inst, IDLoc, Operands)) {
return true;
}
Inst.setLoc(IDLoc);
@@ -4658,7 +4689,7 @@ AMDGPUAsmParser::parseHwregBody(OperandI
skipToken(AsmToken::RParen, "expected a closing parenthesis");
}
-void
+bool
AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,
const int64_t Offset,
const int64_t Width,
@@ -4668,13 +4699,18 @@ AMDGPUAsmParser::validateHwreg(const Ope
if (HwReg.IsSymbolic && !isValidHwreg(HwReg.Id, getSTI())) {
Error(Loc, "specified hardware register is not supported on this GPU");
+ return false;
} else if (!isValidHwreg(HwReg.Id)) {
Error(Loc, "invalid code of hardware register: only 6-bit values are legal");
+ return false;
} else if (!isValidHwregOffset(Offset)) {
Error(Loc, "invalid bit offset: only 5-bit values are legal");
+ return false;
} else if (!isValidHwregWidth(Width)) {
Error(Loc, "invalid bitfield width: only values from 1 to 32 are legal");
+ return false;
}
+ return true;
}
OperandMatchResultTy
@@ -4690,8 +4726,8 @@ AMDGPUAsmParser::parseHwreg(OperandVecto
OperandInfoTy HwReg(ID_UNKNOWN_);
int64_t Offset = OFFSET_DEFAULT_;
int64_t Width = WIDTH_DEFAULT_;
- if (parseHwregBody(HwReg, Offset, Width)) {
- validateHwreg(HwReg, Offset, Width, Loc);
+ if (parseHwregBody(HwReg, Offset, Width) &&
+ validateHwreg(HwReg, Offset, Width, Loc)) {
ImmVal = encodeHwreg(HwReg.Id, Offset, Width);
}
} else if (parseExpr(ImmVal)) {
@@ -5646,11 +5682,7 @@ AMDGPUOperand::Ptr AMDGPUAsmParser::defa
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
}
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetU12() const {
- return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
-}
-
-AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetS13() const {
+AMDGPUOperand::Ptr AMDGPUAsmParser::defaultFlatOffset() const {
return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
}
Modified: llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/FLATInstructions.td Mon Jul 8 07:27:37 2019
@@ -135,17 +135,15 @@ class GlobalSaddrTable <bit is_saddr, st
// saddr is 32-bit (which isn't handled here yet).
class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
bit HasTiedOutput = 0,
- bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
+ bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
opName,
(outs regClass:$vdst),
!con(
!con(
- !con(
- !con((ins VReg_64:$vaddr),
- !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
- (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
- (ins GLC:$glc, SLC:$slc, DLC:$dlc)),
- !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
+ !con((ins VReg_64:$vaddr),
+ !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
+ (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
+ !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
" $vdst, $vaddr"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
let has_data = 0;
let mayLoad = 1;
@@ -159,15 +157,13 @@ class FLAT_Load_Pseudo <string opName, R
}
class FLAT_Store_Pseudo <string opName, RegisterClass vdataClass,
- bit HasSignedOffset = 0, bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
+ bit HasSaddr = 0, bit EnableSaddr = 0> : FLAT_Pseudo<
opName,
(outs),
!con(
- !con(
- !con((ins VReg_64:$vaddr, vdataClass:$vdata),
- !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
- (ins !if(HasSignedOffset,offset_s13,offset_u12):$offset)),
- (ins GLC:$glc, SLC:$slc, DLC:$dlc)),
+ !con((ins VReg_64:$vaddr, vdataClass:$vdata),
+ !if(EnableSaddr, (ins SReg_64:$saddr), (ins))),
+ (ins flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
" $vaddr, $vdata"#!if(HasSaddr, !if(EnableSaddr, ", $saddr", ", off"), "")#"$offset$glc$slc$dlc"> {
let mayLoad = 0;
let mayStore = 1;
@@ -180,18 +176,18 @@ class FLAT_Store_Pseudo <string opName,
multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
let is_flat_global = 1 in {
- def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
+ def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
GlobalSaddrTable<0, opName>;
- def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1, 1>,
+ def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
GlobalSaddrTable<1, opName>;
}
}
multiclass FLAT_Global_Store_Pseudo<string opName, RegisterClass regClass> {
let is_flat_global = 1 in {
- def "" : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
+ def "" : FLAT_Store_Pseudo<opName, regClass, 1>,
GlobalSaddrTable<0, opName>;
- def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1, 1>,
+ def _SADDR : FLAT_Store_Pseudo<opName, regClass, 1, 1>,
GlobalSaddrTable<1, opName>;
}
}
@@ -201,8 +197,8 @@ class FLAT_Scratch_Load_Pseudo <string o
opName,
(outs regClass:$vdst),
!if(EnableSaddr,
- (ins SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
- (ins VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
+ (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
+ (ins VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
" $vdst, "#!if(EnableSaddr, "off", "$vaddr")#!if(EnableSaddr, ", $saddr", ", off")#"$offset$glc$slc$dlc"> {
let has_data = 0;
let mayLoad = 1;
@@ -217,8 +213,8 @@ class FLAT_Scratch_Store_Pseudo <string
opName,
(outs),
!if(EnableSaddr,
- (ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
- (ins vdataClass:$vdata, VGPR_32:$vaddr, offset_s13:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
+ (ins vdataClass:$vdata, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc),
+ (ins vdataClass:$vdata, VGPR_32:$vaddr, flat_offset:$offset, GLC:$glc, SLC:$slc, DLC:$dlc)),
" "#!if(EnableSaddr, "off", "$vaddr")#", $vdata, "#!if(EnableSaddr, "$saddr", "off")#"$offset$glc$slc$dlc"> {
let mayLoad = 0;
let mayStore = 1;
@@ -277,7 +273,7 @@ multiclass FLAT_Atomic_Pseudo<
bit isFP = getIsFP<data_vt>.ret> {
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
- (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
" $vaddr, $vdata$offset$slc">,
GlobalSaddrTable<0, opName>,
AtomicNoRet <opName, 0> {
@@ -287,7 +283,7 @@ multiclass FLAT_Atomic_Pseudo<
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
- (ins VReg_64:$vaddr, data_rc:$vdata, offset_u12:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata$offset glc$slc",
[(set vt:$vdst,
(atomic (FLATAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
@@ -308,7 +304,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_
def "" : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
- (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
" $vaddr, $vdata, off$offset$slc">,
GlobalSaddrTable<0, opName>,
AtomicNoRet <opName, 0> {
@@ -319,7 +315,7 @@ multiclass FLAT_Global_Atomic_Pseudo_NO_
def _SADDR : FLAT_AtomicNoRet_Pseudo <opName,
(outs),
- (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC:$slc),
" $vaddr, $vdata, $saddr$offset$slc">,
GlobalSaddrTable<1, opName>,
AtomicNoRet <opName#"_saddr", 0> {
@@ -341,7 +337,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN
def _RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
- (ins VReg_64:$vaddr, data_rc:$vdata, offset_s13:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, flat_offset:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata, off$offset glc$slc",
[(set vt:$vdst,
(atomic (FLATSignedAtomic i64:$vaddr, i16:$offset, i1:$slc), data_vt:$vdata))]>,
@@ -353,7 +349,7 @@ multiclass FLAT_Global_Atomic_Pseudo_RTN
def _SADDR_RTN : FLAT_AtomicRet_Pseudo <opName,
(outs vdst_rc:$vdst),
- (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, offset_s13:$offset, SLC:$slc),
+ (ins VReg_64:$vaddr, data_rc:$vdata, SReg_64:$saddr, flat_offset:$offset, SLC:$slc),
" $vdst, $vaddr, $vdata, $saddr$offset glc$slc">,
GlobalSaddrTable<1, opName#"_rtn">,
AtomicNoRet <opName#"_saddr", 1> {
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp Mon Jul 8 07:27:37 2019
@@ -71,17 +71,6 @@ void AMDGPUInstPrinter::printU16ImmDecOp
O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
}
-void AMDGPUInstPrinter::printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
- // GFX10: Address offset is 12-bit signed byte offset.
- if (AMDGPU::isGFX10(STI)) {
- O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
- } else {
- O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
- }
-}
-
void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
@@ -128,13 +117,25 @@ void AMDGPUInstPrinter::printOffset(cons
}
}
-void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI,
- raw_ostream &O) {
+void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
uint16_t Imm = MI->getOperand(OpNo).getImm();
if (Imm != 0) {
O << ((OpNo == 0)? "offset:" : " offset:");
- printS13ImmDecOperand(MI, OpNo, STI, O);
+
+ const MCInstrDesc &Desc = MII.get(MI->getOpcode());
+ bool IsFlatSeg = !(Desc.TSFlags & SIInstrFlags::IsNonFlatSeg);
+
+ if (IsFlatSeg) { // Unsigned offset
+ printU16ImmDecOperand(MI, OpNo, O);
+ } else { // Signed offset
+ if (AMDGPU::isGFX10(STI)) {
+ O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
+ } else {
+ O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
+ }
+ }
}
}
Modified: llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h Mon Jul 8 07:27:37 2019
@@ -41,8 +41,6 @@ private:
void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printS13ImmDecOperand(const MCInst *MI, unsigned OpNo,
- const MCSubtargetInfo &STI, raw_ostream &O);
void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
@@ -53,8 +51,8 @@ private:
void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
- void printOffsetS13(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
- raw_ostream &O);
+ void printFlatOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.td Mon Jul 8 07:27:37 2019
@@ -844,21 +844,11 @@ class NamedOperandU8<string Name, AsmOpe
let ParserMatchClass = MatchClass;
}
-class NamedOperandU12<string Name, AsmOperandClass MatchClass> : Operand<i16> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
let PrintMethod = "print"#Name;
let ParserMatchClass = MatchClass;
}
-class NamedOperandS13<string Name, AsmOperandClass MatchClass> : Operand<i16> {
- let PrintMethod = "print"#Name;
- let ParserMatchClass = MatchClass;
-}
-
class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
let PrintMethod = "print"#Name;
let ParserMatchClass = MatchClass;
@@ -876,8 +866,7 @@ def offen : NamedOperandBit<"Offen", Nam
def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
-def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
-def offset_s13 : NamedOperandS13<"OffsetS13", NamedMatchClass<"OffsetS13">>;
+def flat_offset : NamedOperandU16<"FlatOffset", NamedMatchClass<"FlatOffset">>;
def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp Mon Jul 8 07:27:37 2019
@@ -694,7 +694,7 @@ bool isValidHwregWidth(int64_t Width) {
return 0 <= (Width - 1) && isUInt<WIDTH_M1_WIDTH_>(Width - 1);
}
-int64_t encodeHwreg(int64_t Id, int64_t Offset, int64_t Width) {
+uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width) {
return (Id << ID_SHIFT_) |
(Offset << OFFSET_SHIFT_) |
((Width - 1) << WIDTH_M1_SHIFT_);
Modified: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h Mon Jul 8 07:27:37 2019
@@ -439,7 +439,7 @@ LLVM_READNONE
bool isValidHwregWidth(int64_t Width);
LLVM_READNONE
-int64_t encodeHwreg(int64_t Id, int64_t Offset, int64_t Width);
+uint64_t encodeHwreg(uint64_t Id, uint64_t Offset, uint64_t Width);
LLVM_READNONE
StringRef getHwreg(unsigned Id, const MCSubtargetInfo &STI);
Modified: llvm/trunk/test/MC/AMDGPU/flat-gfx10.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-gfx10.s?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-gfx10.s (original)
+++ llvm/trunk/test/MC/AMDGPU/flat-gfx10.s Mon Jul 8 07:27:37 2019
@@ -5,13 +5,13 @@ flat_load_dword v1, v[3:4]
// GFX10: encoding: [0x00,0x00,0x30,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:-1
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: :28: error: expected an 11-bit unsigned offset
flat_load_dword v1, v[3:4] offset:2047
// GFX10: encoding: [0xff,0x07,0x30,0xdc,0x03,0x00,0x7d,0x01]
flat_load_dword v1, v[3:4] offset:2048
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: error: expected an 11-bit unsigned offset
flat_load_dword v1, v[3:4] offset:4 glc
// GFX10: encoding: [0x04,0x00,0x31,0xdc,0x03,0x00,0x7d,0x01]
Modified: llvm/trunk/test/MC/AMDGPU/flat-gfx9.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-gfx9.s?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-gfx9.s (original)
+++ llvm/trunk/test/MC/AMDGPU/flat-gfx9.s Mon Jul 8 07:27:37 2019
@@ -9,39 +9,41 @@ flat_load_dword v1, v[3:4] offset:0
// GCN: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
flat_load_dword v1, v[3:4] offset:-1
-// GCN-ERR: :35: error: failed parsing operand.
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
+// GFX9-ERR: :28: error: expected a 12-bit unsigned offset
// FIXME: Error on VI in wrong column
flat_load_dword v1, v[3:4] offset:4095
// GFX9: flat_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x50,0xdc,0x03,0x00,0x00,0x01]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
flat_load_dword v1, v[3:4] offset:4096
-// GCNERR: :28: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
+// GFX9-ERR: :28: error: expected a 12-bit unsigned offset
flat_load_dword v1, v[3:4] offset:4 glc
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc ; encoding: [0x04,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
flat_load_dword v1, v[3:4] offset:4 glc slc
// GFX9: flat_load_dword v1, v[3:4] offset:4 glc slc ; encoding: [0x04,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
flat_atomic_add v[3:4], v5 offset:8 slc
// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
flat_atomic_add v[3:4], v5 inst_offset:8 slc
// GFX9: flat_atomic_add v[3:4], v5 offset:8 slc ; encoding: [0x08,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :28: error: flat offset modifier is not supported on this GPU
flat_atomic_cmpswap v[1:2], v[3:4] offset:4095
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 ; encoding: [0xff,0x0f,0x04,0xdd,0x01,0x03,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :36: error: flat offset modifier is not supported on this GPU
flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] offset:4095 slc ; encoding: [0xff,0x0f,0x06,0xdd,0x01,0x03,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :36: error: flat offset modifier is not supported on this GPU
flat_atomic_cmpswap v[1:2], v[3:4]
// GFX9: flat_atomic_cmpswap v[1:2], v[3:4] ; encoding: [0x00,0x00,0x04,0xdd,0x01,0x03,0x00,0x00]
@@ -59,11 +61,11 @@ flat_atomic_cmpswap v[1:2], v[3:4] glc
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc ; encoding: [0xff,0x0f,0x05,0xdd,0x01,0x03,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :40: error: flat offset modifier is not supported on this GPU
flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] offset:4095 glc slc ; encoding: [0xff,0x0f,0x07,0xdd,0x01,0x03,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :40: error: flat offset modifier is not supported on this GPU
flat_atomic_cmpswap v0, v[1:2], v[3:4] glc
// GFX9: flat_atomic_cmpswap v0, v[1:2], v[3:4] glc ; encoding: [0x00,0x00,0x05,0xdd,0x01,0x03,0x00,0x00]
@@ -85,11 +87,11 @@ flat_atomic_cmpswap v0, v[1:2], v[3:4] s
flat_atomic_swap v[3:4], v5 offset:16
// GFX9: flat_atomic_swap v[3:4], v5 offset:16 ; encoding: [0x10,0x00,0x00,0xdd,0x03,0x05,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :29: error: flat offset modifier is not supported on this GPU
flat_store_dword v[3:4], v1 offset:16
// GFX9: flat_store_dword v[3:4], v1 offset:16 ; encoding: [0x10,0x00,0x70,0xdc,0x03,0x01,0x00,0x00]
-// VIERR: :1: error: invalid operand for instruction
+// VI-ERR: :29: error: flat offset modifier is not supported on this GPU
flat_store_dword v[3:4], v1, off
// GCNERR: :30: error: invalid operand for instruction
Modified: llvm/trunk/test/MC/AMDGPU/flat-global.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-global.s?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-global.s (original)
+++ llvm/trunk/test/MC/AMDGPU/flat-global.s Mon Jul 8 07:27:37 2019
@@ -92,7 +92,7 @@ global_load_dword v1, v[3:4], off offset
// VI-ERR: :35: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:4095
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: :35: error: expected a 12-bit signed offset
// GFX9: global_load_dword v1, v[3:4], off offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :35: error: not a valid operand.
@@ -102,18 +102,18 @@ global_load_dword v1, v[3:4], off offset
// VI-ERR: :35: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:-4096
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: :35: error: expected a 12-bit signed offset
// GFX9: global_load_dword v1, v[3:4], off offset:-4096 ; encoding: [0x00,0x90,0x50,0xdc,0x03,0x00,0x7f,0x01]
// VI-ERR: :35: error: not a valid operand.
global_load_dword v1, v[3:4], off offset:4096
-// GFX10-ERR: error: invalid operand for instruction
-// GFX9-ERR: :35: error: invalid operand for instruction
+// GFX10-ERR: :35: error: expected a 12-bit signed offset
+// GFX9-ERR: :35: error: expected a 13-bit signed offset
// VI-ERR: :35: error: not a valid operand.
global_load_dword v1, v[3:4] off, offset:-4097
-// GFX10-ERR: error: invalid operand for instruction
-// GFX9-ERR: :35: error: invalid operand for instruction
+// GFX10-ERR: :35: error: expected a 12-bit signed offset
+// GFX9-ERR: :35: error: expected a 13-bit signed offset
// VI-ERR: :35: error: not a valid operand.
global_store_byte v[3:4], v1, off
Modified: llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s?rev=365321&r1=365320&r2=365321&view=diff
==============================================================================
--- llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s (original)
+++ llvm/trunk/test/MC/AMDGPU/flat-scratch-instructions.s Mon Jul 8 07:27:37 2019
@@ -91,9 +91,9 @@ scratch_load_dword v1, v2, off offset:0
// VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:4095
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: :32: error: expected a 12-bit signed offset
// GFX9: scratch_load_dword v1, v2, off offset:4095 ; encoding: [0xff,0x4f,0x50,0xdc,0x02,0x00,0x7f,0x01]
-// VI-ERR: error: not a valid operand.
+// VI-ERR: :32: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-1
// GFX10: encoding: [0xff,0x4f,0x30,0xdc,0x02,0x00,0x7d,0x01]
@@ -101,19 +101,19 @@ scratch_load_dword v1, v2, off offset:-1
// VI-ERR: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-4096
-// GFX10-ERR: error: invalid operand for instruction
+// GFX10-ERR: :32: error: expected a 12-bit signed offset
// GFX9: scratch_load_dword v1, v2, off offset:-4096 ; encoding: [0x00,0x50,0x50,0xdc,0x02,0x00,0x7f,0x01]
-// VI-ERR: error: not a valid operand.
+// VI-ERR: :32: error: not a valid operand.
scratch_load_dword v1, v2, off offset:4096
-// GFX10-ERR: error: invalid operand for instruction
-// GFX9-ERR: error: invalid operand for instruction
-// VI-ERR: error: not a valid operand.
+// GFX10-ERR: :32: error: expected a 12-bit signed offset
+// GFX9-ERR: :32: error: expected a 13-bit signed offset
+// VI-ERR: :32: error: not a valid operand.
scratch_load_dword v1, v2, off offset:-4097
-// GFX10-ERR: error: invalid operand for instruction
-// GFX9-ERR: error: invalid operand for instruction
-// VI-ERR: error: not a valid operand.
+// GFX10-ERR: :32: error: expected a 12-bit signed offset
+// GFX9-ERR: :32: error: expected a 13-bit signed offset
+// VI-ERR: :32: error: not a valid operand.
scratch_store_byte v1, v2, off
// GFX10: encoding: [0x00,0x40,0x60,0xdc,0x01,0x02,0x7d,0x00]
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