[PATCH] D64009: [ARM] MVE: support QQPRRegClass and QQQQPRRegClass

[Mikhail Maltsev via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL364794: [ARM] MVE: support QQPRRegClass and QQQQPRRegClass (authored by miyuki, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D64009?vs=207339&id=207341#toc

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D64009/new/

https://reviews.llvm.org/D64009

Files:
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp


Index: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
@@ -1565,8 +1565,9 @@
   (void)isDivergent;
   // Map v4i64 to QQ registers but do not make the type legal. Similarly map
   // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
-  // load / store 4 to 8 consecutive D registers.
-  if (Subtarget->hasNEON()) {
+  // load / store 4 to 8 consecutive NEON D registers, or 2 to 4 consecutive
+  // MVE Q registers.
+  if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps()) {
     if (VT == MVT::v4i64)
       return &ARM::QQPRRegClass;
     if (VT == MVT::v8i64)


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