[PATCH] D62355: AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D62355#1514932 <https://reviews.llvm.org/D62355#1514932>, @rampitec wrote:

> Where do you get SGPR pair for saveexec if you need to spill an SGPR?


LivePhysRegs takes care of this. Since this is the prologue/epilog, only the ABI registers should be live so it should be easy to find a free register. This will probably require special handling for one of the odd preserve all calling conventions that aren't supported now


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