[PATCH] D61773: [RISCV] Add CFI directives for RISCV prologue/epilog.

Thu May 23 05:47:06 PDT 2019

asb requested changes to this revision.
asb added a comment.
This revision now requires changes to proceed.

Hi @hsiangkai - it seems I applied an old/wip version of my nounwind patch upstream. I've now fixed that in rL361493 <https://reviews.llvm.org/rL361493>. With that, there should be no test changes when implementing this feature.

Please take a look at the two minor suggestions I had on updating frame-info.ll.

================
Comment at: test/CodeGen/RISCV/frame-info.ll:1
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
+
----------------
For completeness, please add a riscv64 RUN line too.

================
Comment at: test/CodeGen/RISCV/frame-info.ll:2
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
+
+define void @foo(i32 signext %size) {
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I think it would be worth generating this with update_llc_test_checks.py. Then you can also see the generated instructions in the CHECK lines which makes it easy to check that the cfi directives match up to the generated stack layout.

Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61773/new/

https://reviews.llvm.org/D61773