[PATCH] D61705: Tablegen type comparison LE should be LT or equal.

Wed May 8 16:21:44 PDT 2019

craig.topper added a comment.

The X86 patterns are probably heavily hidden in tablegen classes, but they should be easily visible in X86GenDAGISel.inc. Does that file generate the same before and after this change?

  /*515111*/    /*Scope*/ 26, /*->515138*/
  /*515112*/      OPC_CheckChild0Type, MVT::v4i32,
  /*515114*/      OPC_SwitchType /*2 cases */, 9, MVT::v16i8,// ->515126
  /*515117*/        OPC_CheckPatternPredicate, 2, // (Subtarget->hasAVX512()) && (Subtarget->hasVLX())
  /*515119*/        OPC_MorphNodeTo1, TARGET_VAL(X86::VPMOVDBZ128rr), 0,
                        MVT::v16i8, 1/*#Ops*/, 0,·
                    // Src: (X86vtrunc:{ *:[v16i8] } VR128X:{ *:[v4i32] }:$src) - Complexity = 3
                    // Dst: (VPMOVDBZ128rr:{ *:[v16i8] } VR128X:{ *:[v4i32] }:$src)

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D61705/new/

https://reviews.llvm.org/D61705