[PATCH] D60706: [ARM] implement 8.1-M instructions at the MC level.

[Simon Tatham via Phabricator via llvm-commits]

simon_tatham created this revision.
simon_tatham added reviewers: dmgreen, samparker, SjoerdMeijer.
Herald added subscribers: llvm-commits, hiraditya, kristof.beyls, javed.absar.
Herald added a project: LLVM.

This commit adds the entire 8.1-M and MVE instruction set.

Most of the new instructions are MVE; those all live in a new tablegen
source file ARMInstrMVE.td. A few FP but non-MVE instructions are
added in ARMInstrVFP.td (VSCCLRM, and loads/stores/moves of a couple
of VFP system registers), and a few non-MVE and non-FP instructions in
ARMInstrThumb2.td (CLRM, the BF and LOL families, and CSEL).

The most complicated thing in the MVE instructions is that a lot of
them take a standard cluster of extra operations to support VPT
predication. Those are defined in ARMInstrFormats.td, under the names
'vpred_n' and 'vpred_r', with a comment explaining what they do.

A change to existing instructions in ARMInstrThumb2.td: tighten up bit
15 of the encodings of lots of normal data processing instructions
like shifted ORR. 8.1-M has reused some of the UNPREDICTABLE space in
those encodings, so now those bits have to be hard requirements.

As well as that, there's a load of supporting stuff in the C++,
supporting new formatting details (AsmPrinter), new register classes
and so on.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D60706

Files:
  llvm/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/lib/Target/ARM/ARMBaseInstrInfo.h
  llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
  llvm/lib/Target/ARM/ARMInstrFormats.td
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
  llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
  llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
  llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
  llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
  llvm/test/CodeGen/ARM/half.ll
  llvm/test/MC/ARM/clrm-asm.s
  llvm/test/MC/ARM/fp-armv8-m.s
  llvm/test/MC/ARM/fp-armv8.s
  llvm/test/MC/ARM/fullfp16.s
  llvm/test/MC/ARM/mve.s
  llvm/test/MC/ARM/no-mve.s
  llvm/test/MC/ARM/ras-extension.s
  llvm/test/MC/ARM/thumbv8.1m-vmrs-vmsr.s
  llvm/test/MC/ARM/thumbv8.1m.s
  llvm/test/MC/ARM/vscclrm-asm.s
  llvm/test/MC/ARM/vstrldr_sys.s
  llvm/test/MC/Disassembler/ARM/clrm.txt
  llvm/test/MC/Disassembler/ARM/mve.s
  llvm/test/MC/Disassembler/ARM/ras-extension-thumb.txt
  llvm/test/MC/Disassembler/ARM/thumb2-v8.1m.txt
  llvm/test/MC/Disassembler/ARM/thumbv8.1m-vmrs-vmsr.txt
  llvm/test/MC/Disassembler/ARM/thumbv8.1m.s
  llvm/test/MC/Disassembler/ARM/vscclrm.txt
  llvm/test/MC/Disassembler/ARM/vstrldr_sys.txt