[PATCH] D60341: [X86] Use (SUBREG_TO_REG (MOV32rm)) for extloadi64i8/extloadi64i16 when the load is 4 byte aligned or better and not volatile.

[Craig Topper via Phabricator via llvm-commits]

craig.topper marked an inline comment as done.
craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/X86/vector-sext-widen.ll:1494
 
 define <4 x i32> @load_sext_4i1_to_4i32(<4 x i1> *%ptr) {
 ; SSE2-LABEL: load_sext_4i1_to_4i32:
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RKSimon wrote:
> I'm a little surprised that <4 x i1> is assumed to have a alignment >= 4
It appears data layout takes element allocation size which I guess is rounded up to a byte, then multiplies by element count.


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https://reviews.llvm.org/D60341