[PATCH] D59626: Add MachineDCE pass after RenameIndependentSubregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 3 inline comments as done.
rampitec added inline comments.


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Comment at: test/CodeGen/X86/combine-bitselect.ll:657
   br label %bb1
 }
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craig.topper wrote:
> This test should be fixed to not be an infinite loop. The middle end wouldn't have given this code to the backend.
Does it change anything? The test has no side effects anyway.
I am not really sure what does it test, so I am a little afraid to touch it. I can add an option not run extra DCE pass here if needed.


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Comment at: test/CodeGen/X86/speculative-load-hardening-indirect.ll:134
 ; X64-NEXT:    sarq $63, %rax
-; X64-NEXT:    movq global_fnptr(%rip), %rcx
+; X64-NEXT:    movq {{.*}}(%rip), %rcx
 ; X64-NEXT:    orq %rax, %rcx
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craig.topper wrote:
> This looks like new regular expressioning the script wasn't doing previously. Can you drop this from this from your diff or rerun the script on an unmodified trunk and commit it.
Will do.


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Comment at: test/CodeGen/X86/tail-dup-merge-loop-headers.ll:262
 
 dead_block:                                       ; preds = %inner_loop_body
   %cmp75.i = icmp ult i8* %dst.0.i, null
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craig.topper wrote:
> This basic block isn't reachable and is keeping other code alive. That would normally have been removed by IR passes.
Do I conclude x86 does not really need this pass, since most of the stuff can be handled separatetly, like speculative load hardening?
If that is the case I can only enable it if subreg liveness is enabled, like proposed earlier.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59626/new/

https://reviews.llvm.org/D59626