[PATCH] D59626: Add MachineDCE pass after RenameIndependentSubregs

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/combine-bitselect.ll:657
   br label %bb1
 }
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This test should be fixed to not be an infinite loop. The middle end wouldn't have given this code to the backend.


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Comment at: test/CodeGen/X86/speculative-load-hardening-gather.ll:10
 ; CHECK-NEXT:    movq %rsp, %rax
-; CHECK-NEXT:    movq $-1, %rcx
 ; CHECK-NEXT:    sarq $63, %rax
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This looks like speculative load hardening is creating an instruction it doesn't end up using. The speculative loading hardening pass runs after the previous times the MachineDCE was ran. Maybe we should fix the pass to not insert dead instructions.


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Comment at: test/CodeGen/X86/speculative-load-hardening-indirect.ll:134
 ; X64-NEXT:    sarq $63, %rax
-; X64-NEXT:    movq global_fnptr(%rip), %rcx
+; X64-NEXT:    movq {{.*}}(%rip), %rcx
 ; X64-NEXT:    orq %rax, %rcx
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This looks like new regular expressioning the script wasn't doing previously. Can you drop this from this from your diff or rerun the script on an unmodified trunk and commit it.


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Comment at: test/CodeGen/X86/tail-dup-merge-loop-headers.ll:262
 
 dead_block:                                       ; preds = %inner_loop_body
   %cmp75.i = icmp ult i8* %dst.0.i, null
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This basic block isn't reachable and is keeping other code alive. That would normally have been removed by IR passes.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D59626/new/

https://reviews.llvm.org/D59626