[PATCH] D59201: [RegAllocHints] Avoid compile time regression

[Quentin Colombet via llvm-commits]

> On Mar 11, 2019, at 12:16 PM, Jonas Paulsson via Phabricator via llvm-commits <llvm-commits at lists.llvm.org> wrote:
> 
> jonpa marked an inline comment as done.
> jonpa added inline comments.
> 
> 
> ================
> Comment at: test/CodeGen/X86/regalloc-copy-hints.mir:308
> +  attributes #0 = { "target-cpu"="i486" }
> +  attributes #1 = { nounwind }
> +
> ----------------
> qcolombet wrote:
>> Do we need the IR part?
>> (I.e., does anything in the MIR reference back the IR?)
> I tried removing it but then got 'basic block "bb' is not defined in the function 'fun'"…?

For that you need to remove the "IR links” from the machine block to the IR block.
The machine block names look like this:
bb.#MachineID[.nameOfIRBasicBlock]
In other words, delete the part after the number for each basic block.

I see that you have memory operands (the things that look like `:: (load...)`) too and if they are not optional, you’ll need to keep some IR anyway.

> 
> 
> CHANGES SINCE LAST ACTION
>  https://reviews.llvm.org/D59201/new/
> 
> https://reviews.llvm.org/D59201
> 
> 
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