[PATCH] D58911: DAG: Don't break value dependencies when sorting loads by offset

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: bogner, rampitec, cfang, sunfish.
Herald added subscribers: mgrang, tpr, nhaehnle, wdng, jvesely, MatzeB.

AMDGPU has some load instructions that write into the high bits of the
destination register, and have a tied input for the low input
 bits. These can easily have the same base pointer, but be a swizzle so
the high address load needs to come first. This was inserting glue
forcing the opposite ordering, producing a cycle the InstrEmitter
would assert on. Consider if two loads depend on each other before
sorting them.

      

Fixes bug 40936 by reverting r351379, which added a hacky attempt to
fix this by adding chains in this case, which I think was just working
around broken glue before the InstrEmitter. The core of the patch is
re-implementing the fix for that problem.


https://reviews.llvm.org/D58911

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
  lib/Target/AMDGPU/SIISelLowering.cpp
  test/CodeGen/AMDGPU/chain-hi-to-lo.ll

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