[PATCH] D57044: [AArch64] OOptimize floating point materialization

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5451
+              AArch64_AM::isLogicalImmediate(ImmInt.getZExtValue(),
+                                             VT.getSizeInBits());
 
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zatrazz wrote:
> efriedma wrote:
> > I have no idea what isLogicalImmediate does if the RegSize is 16.
> My understanding it should be safe since fmov transfer for float16 will be done from 32 bit register.
The proposed transform is fine for f16; I'm more concerned that isLogicalImmediate() itself won't return the right result, since the actual underlying operation is a 32-bit orr.

Actually, thinking about it a bit more, we might as well just mark ISD::ConstantFP Legal for f16, since it can always be done in two instructions.

On a related note, not sure the ISel patterns you need for f16 are implemented.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D57044/new/

https://reviews.llvm.org/D57044