[PATCH] D57056: [MC][X86] Correctly model additional operand latency caused by transfer delays from the integer to the floating point unit.

[Matt Davis via Phabricator via llvm-commits]

mattd added a comment.

LGTM.  I'd wait a bit to see if others have anything else to add.



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Comment at: include/llvm/MC/MCSchedule.h:375
+  /// writes of scheduling class WriteResourceIdx.
+  static unsigned getForwardingDelayCycles(ArrayRef<MCReadAdvanceEntry> Entries,
+                                           unsigned WriteResourceIdx = 0);
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You can probably constify Entries.


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Comment at: lib/Target/X86/X86Schedule.td:19
 def ReadAfterVecYLd : SchedRead;
 
+def ReadInt2Fpu : SchedRead;
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I think it would be helpful to have a comment here, describing  ReadInt2Fpu.  Something similar to what you described above in the Details.


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  https://reviews.llvm.org/D57056/new/

https://reviews.llvm.org/D57056