[PATCH] D56201: [LegalizeVectorTypes] Allow single loads and stores for more short vectors

[Guillaume Marques via Phabricator via llvm-commits]

tauril updated this revision to Diff 181556.
tauril added a comment.

I modified some AMDGPU tests to track more registers where possible as @jvesely suggested, and I added some missing new relevant generated instructions (`BFE_INT`).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56201/new/

https://reviews.llvm.org/D56201

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  test/CodeGen/AMDGPU/load-constant-i16.ll
  test/CodeGen/AMDGPU/load-global-i16.ll
  test/CodeGen/AMDGPU/load-local-i16.ll
  test/CodeGen/X86/load-local-i1.ll
  test/CodeGen/X86/widen_arith-3.ll
  test/CodeGen/X86/widen_cast-2.ll
  test/CodeGen/X86/widen_cast-3.ll
  test/CodeGen/X86/widen_load-2.ll

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