[PATCH] D56156: [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them.

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 179770.
craig.topper added a comment.

Rebase. Looks like this is a regression on sse4.1 on setcc-combine.ll. I'll work on a follow up patch for that.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D56156/new/

https://reviews.llvm.org/D56156

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/PowerPC/f128-truncateNconv.ll
  test/CodeGen/PowerPC/ppc64-P9-setb.ll
  test/CodeGen/X86/setcc-combine.ll
  test/CodeGen/X86/vsel-cmp-load.ll

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