[PATCH] D56156: [DAGCombiner][X86][PowerPC] Teach visitSIGN_EXTEND_INREG to fold (sext_in_reg (aext/sext x)) -> (sext x) when x has more than 1 sign bit and the sext_inreg is from one of them.

Mon Dec 31 07:55:52 PST 2018

RKSimon added inline comments.

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Comment at: test/CodeGen/X86/setcc-combine.ll:2
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic < %s | FileCheck %s

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Please can you replace the -mcpu with -mattr=+sse2/sse41 variants to prove that the codegen changes are different if we have suitable pextrd support?

Repository:
  rL LLVM

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  https://reviews.llvm.org/D56156/new/

https://reviews.llvm.org/D56156