[PATCH] D55380: [AMDGPU] Shrink scalar AND, OR, XOR instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:515
 
+      // Attempt to shink AND/OR/XOR operations requiring non-inlineable literals.
+      // For AND or OR, try using S_BITSET{0,1} to clear or set bits.
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This loop is starting to get big, can you move this to a function?


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Comment at: lib/Target/AMDGPU/SIShrinkInstructions.cpp:529-532
+        if (!Src0->isReg() && Src1->isReg()) {
+          SrcReg = Src1;
+          SrcImm = Src0;
+        }
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Is there any real reason you need to handle this? Constants are canonicalized to the RHS (we just undo this for VALU instructions because that's the only way to shrink)


Repository:
  rL LLVM

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D55380/new/

https://reviews.llvm.org/D55380