[PATCH] D55380: [AMDGPU] Shrink scalar AND, OR, XOR instructions

[Graham Sellers via Phabricator via llvm-commits]

grahamsellers created this revision.
grahamsellers added reviewers: arsenm, nhaehnle.
Herald added subscribers: llvm-commits, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.

This change attempts to shrink scalar AND, OR and XOR instructions which take an immediate that isn't inlineable.

It performs:
 AND s0, s0, ~(1 << n) -> BITSET0 s0, n
 OR s0, s0, (1 << n) -> BITSET1 s0, n
 AND s0, s1, x -> ANDN2 s0, s1, ~x
 OR s0, s1, x -> ORN2 s0, s1, ~x
 XOR s0, s1, x -> XNOR s0, s1, ~x

In particular, this catches setting and clearing the sign bit for fabs (and x, 0x7ffffffff -> bitset0 x, 31 and or x, 0x80000000 -> bitset1 x, 31).


Repository:
  rL LLVM

https://reviews.llvm.org/D55380

Files:
  lib/Target/AMDGPU/SIShrinkInstructions.cpp
  test/CodeGen/AMDGPU/andorbitset.ll
  test/CodeGen/AMDGPU/andorxorinvimm.ll
  test/CodeGen/AMDGPU/fabs.ll
  test/CodeGen/AMDGPU/fneg-fabs.ll
  test/CodeGen/AMDGPU/gep-address-space.ll
  test/CodeGen/AMDGPU/local-64.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D55380.177018.patch
Type: text/x-patch
Size: 11601 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181206/7f863e86/attachment.bin>