[PATCH] D54663: [PowerPC] Complete the custom legalization of vector int to fp conversion

[Roland Froese via Phabricator via llvm-commits]

RolandF added inline comments.


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Comment at: lib/Target/PowerPC/PPCISelLowering.cpp:7333
+    Arrange = DAG.getBitcast(IntermediateVT, Arrange);
+    Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange,
+                         DAG.getValueType(Op.getOperand(0).getValueType()));
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nemanjai wrote:
> RolandF wrote:
> > When I looked at this before, I found that using SIGN_EXTEND_INREG led to a perm/shift left/shift right pattern, and I thought that using unpack would be faster for the signed int/pwr8 case.
> Ah cool, I didn't think of that. You're right an unpack is definitely useful for something like this (unpack low for LE and high for BE).
> However, I think that would be good to do irrespective of this and in a follow-up patch.
> What I'm getting at is that however the pertinent pattern such as:
> `sign_extend_inreg (vector_shuffle ...)`
> came into existence, it's good to emit optimal code for it.
Sure, makes sense.


Repository:
  rL LLVM

https://reviews.llvm.org/D54663