[PATCH] D54648: [TableGen] Emit more variant transitions

[Andrea Di Biagio via Phabricator via llvm-commits]

andreadb accepted this revision.
andreadb added a comment.
This revision is now accepted and ready to land.

In https://reviews.llvm.org/D54648#1305567, @evandro wrote:

> The issue that I'm trying to avoid is that it's not enough for me to add predicates based on `MCSchedPredicate` for Exynos processors is other processors don't.  Then, if an instruction that I model by using a variant schedule is also modeled by another processor, `TableGen` will emit no solution at all for the instruction.  This patch, which I recognize is just an attempt, aims at allowing the proper solution for a processor using such predicates, while indeed resulting in a clumsy solution the scheduling of the same instruction for other processors.
>
> The issue is that it's virtually impossible at the moment to model AArch64 without running on `llvm-mca` giving right up.  I was thinking that instead of giving up, `llvm-mca` should resort to a reasobale default and highlight it in its result.  I proposed `NoSchedPred` as this default, but, though we can discuss what the default should be, I think that no default does not make sense as is.


Right. I see what you mean.

I was under the impression that transitions would have been correctly expanded at least for your Exynos models.
However, it seems like the lack of MCSchedPredicates in other processor models is somehow causing problems.. If that's the case, then I think your patch makes sense.
Although it is not idea, at least, it unblocks your work.

Could you add a brief comment (a FIXME ) in the code, and the XFAIL test to explain what is happening (and why we are less strict with the check)?
We may want to revisit this in future. But for now, your patch is a good starting point.

Thanks!
-Andrea


https://reviews.llvm.org/D54648