[PATCH] D54648: [TableGen] Emit more variant transitions

[Evandro Menezes via Phabricator via llvm-commits]

evandro added a comment.

The issue that I'm trying to avoid is that it's not enough for me to add predicates based on `MCSchedPredicate` for Exynos processors is other processors don't.  Then, if an instruction that I model by using a variant schedule is also modeled by another processor, `TableGen` will emit no solution at all for the instruction.  This patch, which I recognize is just an attempt, aims at allowing the proper solution for a processor using such predicates, while indeed resulting in a clumsy solution the scheduling of the same instruction for other processors.

The issue is that it's virtually impossible at the moment to model AArch64 without running on `llvm-mca` giving right up.  I was thinking that instead of giving up, `llvm-mca` should resort to a reasobale default and highlight it in its result.  I proposed `NoSchedPred` as this default, but, though we can discuss what the default should be, I think that no default does not make sense as is.


https://reviews.llvm.org/D54648