[PATCH] D54714: [AMDGPU] Add and update scalar instructions

[Graham Sellers via Phabricator via llvm-commits]

grahamsellers created this revision.
grahamsellers added reviewers: nhaehnle, arsenm.
Herald added subscribers: llvm-commits, t-tye, tpr, dstuttard, yaxunl, wdng, jvesely, kzhuravl.

This patch adds support for S_ANDN2, S_ORN2 32-bit and 64-bit instructions and adds splits to move them to the vector unit (for which there is no equivalent instruction). It modifies the way that the more complex scalar instructions are lowered to vector instructions by first breaking them down to sequences of simpler scalar instructions which are then lowered through the existing code paths. The pattern for S_XNOR has also been updated to apply inversion to one input rather than the output of the XOR as the result is equivalent and may allow leaving the NOT instruction on the scalar unit.

A new test for NAND has been added, and existing tests now hit the new instructions (and have been modified accordingly). More tests are forthcoming in an update to this patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D54714

Files:
  lib/Target/AMDGPU/AMDGPUInstructions.td
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SOPInstructions.td
  test/CodeGen/AMDGPU/constant-fold-mi-operands.ll
  test/CodeGen/AMDGPU/fceil64.ll
  test/CodeGen/AMDGPU/ftrunc.f64.ll
  test/CodeGen/AMDGPU/insert_vector_elt.ll
  test/CodeGen/AMDGPU/nand.ll
  test/CodeGen/AMDGPU/xnor.ll

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