[PATCH] D54218: [MachineScheduler] Bias physical register immediate assignments

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

Looks reasonable to me.
Could of comments/nitpicks inlined.



================
Comment at: llvm/lib/CodeGen/MachineScheduler.cpp:2878
+           TargetRegisterInfo::isPhysicalRegister(MI->getOperand(0).isReg()))
+      return isTop ? -1 : 1;
+  }
----------------
In case this instruction has more than one definition, should we check all of them?


================
Comment at: llvm/lib/CodeGen/MachineScheduler.cpp:3210
                DAG->dumpNode(*Dep.getSUnit()));
+    //assert(!Copy->isMoveImmediate());
     DAG->moveInstruction(Copy, InsertPos);
----------------
Dead comment.


Repository:
  rL LLVM

https://reviews.llvm.org/D54218