[PATCH] D53291: add riscv32e to the llvm

[Daliang Xu via Phabricator via llvm-commits]

xudaliang.pku added a comment.

In https://reviews.llvm.org/D53291#1266087, @brucehoult wrote:

> In https://reviews.llvm.org/D53291#1266082, @kito-cheng wrote:
>
> > rv32e arch and ilp32e ABI is decoupling is GCC, that's mean rv32i with ilp32e is possible, so I would suggest separate two thing.
>
>
> Very true.
>
> In embedded systems it can often make sense to use the ilp32e ABI even on CPUs with 32 registers because there are significantly fewer argument and temporary registers, making interrupt response time shorter. All the high 16 registers are callee-save, which means you can use them if required but you need to save them first and restore them after.


Thanks for your advice.
I think decouple the rv32e and ilp32e is great. I have not considered it before. I will do it later.
But, I was not sure what rv32e and ilp32e really meaans. There is still something not clearly.  Is the march rv32e only means that the regs only contains x0-x15 ?  And the ABI ilp32e means Stack Alignment and calling convention, etc (see in https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md#rv32e-calling-convention )?


Repository:
  rL LLVM

https://reviews.llvm.org/D53291