[PATCH] D48131: [RISCV] Implement codegen for cmpxchg on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


================
Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:1705
+  Function *MaskedCmpXchg = Intrinsic::getDeclaration(
+      CI->getModule(), Intrinsic::riscv_masked_cmpxchg_i32, Tys);
+  return Builder.CreateCall(MaskedCmpXchg,
----------------
rogfer01 wrote:
> @asb, I have a minor question here:
> 
> At some point we will want to implement this for rv64a. I presume that for rv64a we still want to have `setMinCmpXchgSizeInBits(32)` so the `i32` and the `i64` cases are handled in `RISCVExpandPseudoInsts.cpp` as non-masked lr/sc loops. Currently `AtomicExpand.cpp` will choose to use the smaller size supported (`i32`) and the intrinsic here will be using `i32` values. This will require some form of legalisation in 64-bit, won't it? Will we end custom legalising this intrinsic call for the 64-bit case to a `riscv_masked_cmpxchg_i64`? Or perhaps there is a neater way to achieve this?
> 
> Thanks!
Hi Roger. If i64 is the only legal type, I don't see a way around having an i64 form of the intrinsic. You then need to promote the operands to i64.

So you want to do something like


```
unsigned XLen = Subtarget.getXLen();
Value *Ordering = Builder.getIntN(XLen, static_cast<uint64_t>(Ord));
```

and use Builder.CreateSExt on the other operands.


https://reviews.llvm.org/D48131