[PATCH] D51502: [X86] Fix register resizings for inline assembly register operands.

[Nirav Davé via llvm-commits]

Yes, this is a fix to match GCC's register assignment for a 64-bit in
32-bit mode to pairs of registers.

I haven't looked too deeply into the details, but register allocation order
is sensitive to the register classes (I think by way of register pressure)
which is why the additional register classes are able to change our
selection bias between 32-bit registers and 8-bits.


On Mon, Sep 17, 2018 at 2:43 PM, Matthias Braun via Phabricator <
reviews at reviews.llvm.org> wrote:

> MatzeB added a comment.
>
> Isn't this fix about inline assembly? Why do we see all the
> scheduling/regalloc changes here?
>
>
> Repository:
>   rL LLVM
>
> https://reviews.llvm.org/D51502
>
>
>
>
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