[PATCH] D51308: MachineVerifier: Fix assert on implicit virtreg use

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added a reviewer: MatzeB.
Herald added subscribers: nhaehnle, wdng, jvesely.

If the liveness of a physical register was invalid, this
was attempting to iterate the subregisters of all register
uses of the instruction, which would assert when it
encountered an implicit virtual register operand.


https://reviews.llvm.org/D51308

Files:
  lib/CodeGen/MachineVerifier.cpp
  test/CodeGen/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir


Index: test/CodeGen/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
@@ -0,0 +1,21 @@
+# RUN: not llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s
+
+# When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use.
+
+
+# ERROR: *** Bad machine code: Using an undefined physical register ***
+# ERROR: instruction: S_ENDPGM implicit %0:vgpr_32, implicit $vcc
+# ERROR: operand 1:   implicit $vcc
+
+...
+
+name: invalid_implicit_physreg_use_with_implicit_virtreg
+tracksRegLiveness: true
+
+body:             |
+  bb.0:
+    %0:vgpr_32 = IMPLICIT_DEF
+    S_ENDPGM implicit %0, implicit $vcc
+
+...
+
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -1533,10 +1533,12 @@
         // get a report for its operand.
         if (Bad) {
           for (const MachineOperand &MOP : MI->uses()) {
-            if (!MOP.isReg())
+            if (!MOP.isReg() || !MOP.isImplicit())
               continue;
-            if (!MOP.isImplicit())
+
+            if (!TargetRegisterInfo::isPhysicalRegister(MOP.getReg()))
               continue;
+
             for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
                  ++SubRegs) {
               if (*SubRegs == Reg) {


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