[PATCH] D51254: [X86] Replace support for vXi32 SMUL_LOHI/UMUL_LOHI with MULHS/MULHU support instead.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel.

The only time vector SMUL_LOHI/UMUL_LOHI nodes are created is during division/remainder lowering. If its created before op legalization, generic DAGCombine immediately turns that SMUL_LOHI/UMUL_LOHI into a MULHS/MULHU since only the upper half is used. That node will stick around through vector op legalization and will be turned back into UMUL_LOHI/SMUL_LOHI during op legalization. It will then be custom lowered by the X86 backend. Due to this two step lowering the vector shuffles created by the custom lowering get legalized after their inputs rather than before. This prevents the shuffles from being combined with any build_vector of constants.

This patch uses changes vXi32 to use MULHS/MULHU instead. This is what the later DAG combine did anyway. But by skipping the change back to UMUL_LOHI/SMUL_LOHI we lower it before any constant BUILD_VECTORS. This allows the vector_shuffle creation to constant fold with the build_vectors. This accounts for the test changes here.


Repository:
  rL LLVM

https://reviews.llvm.org/D51254

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/vector-idiv-sdiv-128.ll
  test/CodeGen/X86/vector-idiv-sdiv-256.ll
  test/CodeGen/X86/vector-idiv-sdiv-512.ll
  test/CodeGen/X86/vector-idiv-udiv-128.ll
  test/CodeGen/X86/vector-idiv-udiv-256.ll
  test/CodeGen/X86/vector-idiv-udiv-512.ll
  test/CodeGen/X86/vector-idiv.ll
  test/CodeGen/X86/vselect-avx.ll

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