[PATCH] D48725: [SLP] Vectorize bit-parallel operations with SWAR.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> 128 is not the smallest vector, because we can do partial load/stores

Essentially, yes.

> Actually I don't think the current case can be handled in the same way as MatchLoadCombine: in the case the MatchLoadCombine, the "or" instruction provides a way to link the stores together.

We have code to do this sort of merging in DAGCombiner::MergeConsecutiveStores.  But it misses cases like the ones in your patch because combiner-global-alias-analysis is off by default. (I don't remember the full history of that, but IIRC the compile-time penalty was too large.)


Repository:
  rL LLVM

https://reviews.llvm.org/D48725