[llvm] r336084 - [Mips][FastISel] Do not duplicate condition while lowering branches

[Petar Jovanovic via llvm-commits]

Author: petarj
Date: Mon Jul  2 01:56:57 2018
New Revision: 336084

URL: http://llvm.org/viewvc/llvm-project?rev=336084&view=rev
Log:
[Mips][FastISel] Do not duplicate condition while lowering branches

This change fixes the issue that arises when we duplicate condition from
the predecessor block. If the condition's arguments are not considered alive
across the blocks, fast regalloc gets confused and starts generating reloads
from the slots that have never been spilled to. This change also leads to
smaller code given that, unlike on architectures with condition codes, on
Mips we can branch directly on register value, thus we gain nothing by
duplication.

Patch by Dragan Mladjenovic.

Differential Revision: https://reviews.llvm.org/D48642

Added:
    llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsFastISel.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=336084&r1=336083&r2=336084&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Mon Jul  2 01:56:57 2018
@@ -951,12 +951,9 @@ bool MipsFastISel::selectBranch(const In
   //
   MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
   MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
-  BI->getCondition();
   // For now, just try the simplest case where it's fed by a compare.
   if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
-    unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
-    if (!emitCmp(CondReg, CI))
-      return false;
+    unsigned CondReg = getRegForValue(CI);
     BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
         .addReg(CondReg)
         .addMBB(TBB);

Added: llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll?rev=336084&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/icmpbr1.ll Mon Jul  2 01:56:57 2018
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
+; RUN:     < %s -verify-machineinstrs | FileCheck %s
+
+
+define i32 @foobar(i32*) {
+bb0:
+; CHECK-LABEL: foobar:
+; CHECK:       # %bb.0: # %bb0
+; CHECK:        lw $[[REG0:[0-9]+]], 0($4)
+; CHECK-NEXT:   sltiu $[[REG1:[0-9]+]], $[[REG0]], 1
+; CHECK:        sw $[[REG1]], [[SPILL:[0-9]+]]($sp) # 4-byte Folded Spill
+  %1 = load  i32, i32* %0 , align 4
+  %2 = icmp eq i32 %1, 0
+  store atomic i32 0, i32* %0 monotonic, align 4
+  br label %bb1
+bb1:
+; CHECK:       # %bb.1: # %bb1
+; CHECK-NEXT:    lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload
+; CHECK-NEXT:    bgtz $[[REG2]], $BB0_3
+  br i1 %2, label %bb2, label %bb3
+bb2:
+; CHECK:         $BB0_3: # %bb2
+; CHECK-NEXT:    addiu $2, $zero, 1
+  ret i32 1
+bb3:
+  ret i32 0
+}