[PATCH] D48832: [ARM] ARMCodeGenPrepare backend pass

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 2 13:05:55 PDT 2018


efriedma added a comment.

Not a complete review, but a quick first pass.

On a sort of related note, I ran into an issue recently with a testcase like the following: "void a(short *x, void f()) { if (*x == -3) f(); }".  We generate an extra instruction because we treat the loaded value as unsigned.  Not sure if that's in scope for the sort of thing you want to fix with this IR pass.



================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:113
+
+static bool isSigned(Value *V) {
+  if (auto *I = dyn_cast<Instruction>(V)) {
----------------
Please add a comment explaining what it means for an instruction to be "signed".


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:280
+  case Instruction::Add:
+    return TypeSize == 16 ? Intrinsic::arm_uadd16 :
+      Intrinsic::arm_uadd8;
----------------
Is it safe to generate calls to uadd?  It writes to the GE bits, and user code could potentially read them.


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:441
+bool ARMCodeGenPrepare::isNarrowInstSupported(Instruction *I) {
+  if (!ST->hasDSP() || DisableDSP || !isSupportedType(I))
+    return false;
----------------
Do we need to check we have Thumb2, if we're in Thumb mode?


https://reviews.llvm.org/D48832





More information about the llvm-commits mailing list