[PATCH] D48832: [ARM] ARMCodeGenPrepare backend pass

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:10
+//
+/// \file
+/// This pass inserts intrinsics to handle small types that would otherwise be
----------------
It may be good to copy the description you have of the algorithm in the commit message to here (or something similar)


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:134
+
+/// Some instructions can 8- and 16-bit operands, and we don't need to promote
+/// anything larger. We disallow booleans to make life easier when dealing with
----------------
nitpick. Typo or missing word "Some instructions can 8- and 16 .."


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:198
+
+/// Return true is the given value is a leaf that will need to be zext'd.
+static bool isSource(Value *V) {
----------------
Typo : "is the given.." => "if the given.."


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:220
+
+/// Return whether will can safely mutate V's type to ExtTy without having
+/// to be concerned with zero extending or truncation.
----------------
Typo "will" => "we"


================
Comment at: lib/Target/ARM/ARMCodeGenPrepare.cpp:269
+
+/// Return the intrinsic for the instruction that can performed the same
+/// operation but on a narrow type. This is using the parallel dsp intrinsics
----------------
typo - "performed"


================
Comment at: test/CodeGen/ARM/arm-cgp-signed.ll:1
+; RUN: llc -mtriple=thumbv7m %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s
----------------
Please add a line to describe overall what this test is about


https://reviews.llvm.org/D48832