[PATCH] D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8, i16} on RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: jyknight, jfb, eli.friedman, theraven.
Herald added subscribers: rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
asb added a dependency: D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A.

The 32-bit AMO{ADD,OR,XOR}_W instructions can be used to implement 8/16-bit AMOs with appropriate manipulation of the operands. This is preferable to creating an LL/SC loop and using the generic path for RISC-V masked atomicrmw codegen.

There is an argument for merging with https://reviews.llvm.org/D47882, but there seemed merit in keeping it separate given that this is an optimisation on top of the more generic lowering strategy path which is being reviewed in that patch.


https://reviews.llvm.org/D48129

Files:
  include/llvm/IR/IntrinsicsRISCV.td
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfoA.td
  test/CodeGen/RISCV/atomic-rmw.ll

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