[PATCH] D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 151167.
asb edited the summary of this revision.
asb added a comment.

Updates:

- Expand masked AMOs to IR for address calculation and masking + an intrinsic for the core LL/SC loop. Introduce a new hook in TargetLowering to allow this
- Support for part-word atomicrmw max/min/umax/umin
- Use MaskedMerge <https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge> rather than calculating an inverse mask
- Expand atomicrmw sub i32 to (AMOADD_W GPR:$addr, (SUB X0, GPR:$incr)) with appropriate AQ/RL bits

If there is enthusiasm from other targets, it may be worth moving more of the logic in RISCVISelLowering::emitAtomicRMW to AtomicExpandPass. As evidenced in the follow-up patch which supports 8/16-bit bitwise AMOs with 32-bit AMOs, it is useful to retain the ability to provide custom expansion logic.

I've authored an RFC which details the strategy which I'll post as soon as I've completed uploading the patch-set.


https://reviews.llvm.org/D47882

Files:
  include/llvm/CodeGen/TargetLowering.h
  include/llvm/IR/Intrinsics.td
  include/llvm/IR/IntrinsicsRISCV.td
  lib/CodeGen/AtomicExpandPass.cpp
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoA.td
  lib/Target/RISCV/RISCVTargetMachine.cpp
  test/CodeGen/RISCV/atomic-rmw.ll

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