[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[James Y Knight via Phabricator via llvm-commits]

jyknight added a comment.

fence.tso is in the draft spec you linked to -- are you not using it because it hasn't been finalized, or was it just added after you left that comment?



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Comment at: test/CodeGen/RISCV/atomic-rmw.ll:495-496
+
+; Don't test for i8 atomicrmw {min,max,umin,umax} as Clang won't generate it
+; and we don't currently intend to support these with RV32A.
+
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I think we ought to support these -- they're not much harder to implement than nand, I think. But I'll leave a comment on the other patch.


https://reviews.llvm.org/D47587